Display devices in which each pixel includes a plurality of subpixels so that viewing angle characteristics of display are improved are widely known.
FIG. 18 illustrates a configuration of a pixel PIX100 provided in an active matrix liquid crystal display device, which is an example of such display devices (see Patent Literature 1 for example).
The pixel PIX100 is provided corresponding to each intersection of a scanning line Gi (i is an integer indicative of an ordinal number of each scanning line) and a data line Sj (j is an integer indicative of an ordinal number of each data line). The pixel PIX100 is constituted by two subpixels PIXa and PIXb that are different from each other in threshold voltage. Since the single pixel PIX100 is divided into two subpixels, i.e., the subpixel PIXa and the subpixel PIXb, distortion of a T-V (transmittance-voltage) characteristic of a liquid crystal layer is distributed between the subpixel PIXa and the subpixel PIXb, as described in Patent Literature 1. This makes it possible to suppress a phenomenon in which an image becomes whitish when viewed from an oblique angle. As a result, viewing angle characteristics can be improved.
The subpixel PIXa includes a transistor T101, a liquid crystal capacitor ClcA, and a storage capacitor CstA. The subpixel PIXb includes transistors T102 and T103, a liquid crystal capacitor ClcB, a storage capacitor CstB, and a buffer capacitor Cdown.
Each of the transistors T101, T102, and T103 is a TFT (Thin Film Transistor). All of the thin film transistors (hereinafter referred to as TFTs) in the pixel PIX100 are n-type TFTs. Generally, which of two terminals of an n-type TFT becomes a source terminal and which of the two terminals becomes a drain terminal depend on voltages applied to the respective terminals. Specifically, out of the two terminals, a terminal to which a smaller voltage is applied becomes a source terminal, and a terminal to which a larger voltage is applied becomes a drain terminal. However, description of an operation of a pixel circuit becomes complicated if the terminals are differently referred to depending on relationships between the voltages. Therefore, for convenience of description, even if a relationship between the voltages changes and thereby a relationship between the source and drain terminals changes, the terminals are referred to by identical terms to those first given, unless otherwise specified. The same applies to the Embodiments below.
In the subpixel PIXa, a gate terminal of the transistor T101 is connected to the scanning line Gi, a source terminal of the transistor T101 is connected to the data line Sj, and a drain terminal of the transistor T101 is connected to a node na. The liquid crystal capacitor ClcA is formed between the node na and a common electrode com101. The storage capacitor CstA is connected between the node na and a common electrode com2. To the common electrode com101, an electric potential Vcom101 is applied, and to the common electrode com102, an electric potential Vcom102 is applied. The electric potential Vcom101 is a DC electric potential (direct current electric potential).
In the subpixel PIXb, a gate terminal of the transistor T102 is connected to the scanning line Gi, a source terminal of the transistor T102 is connected to the data line Sj, and a drain terminal of the transistor T102 is connected to a node nb. The liquid crystal capacitor ClcB is formed between the node nb and the common electrode com1. The storage capacitor CstB is connected between the node nb and the common electrode com2. A gate terminal of the transistor T103 is connected to a scanning line Gi+1, a source terminal of the transistor T103 is connected to the node nb, and a drain terminal of the transistor T103 is connected to a node nc. The buffer capacitor Cdown is connected between the node nc and the common electrode com102.
Next, FIG. 19 illustrates a timing chart explaining a circuit operation of the pixel PIX100. It is assumed that the pixel PIX100 is driven according to data line inversion driving since a current liquid crystal panel is generally AC driven. This applies throughout this specification. The following describes a circuit operation of the pixel PIX100 with reference to the timing chart of FIG. 19. FIG. 19 illustrates an example in which electric potential waveforms of the nodes na, nb, and nc are ones achieved in a case where i=2 is satisfied. Further, FIG. 19 illustrates a case where a waveform of a data electric potential is one achieved in a case where j=1 (i.e., odd number) is satisfied. Note that in a case where j is an even number, the data electric potential has a waveform having a polarity reverse to that of the waveform achieved in a case where j is an odd number. The circuit diagrams of FIGS. 20 through 23 for explaining respective states of the pixel PIX100 are also referred to.
It is assumed that, in a first frame, an electric potential that is equal to or higher than the electric potential Vcom101 is applied to the node na and the node nb during light emission of the liquid crystal panel. That is, it is assumed that a voltage (liquid crystal applied voltage) of a positive polarity is applied between the node na and the common electrode com101 and between the node nb and the common electrode com101. Since the electric potential Vcom101 is a DC electric potential, an electric potential Vdata supplied from a data driver to the data line S1 has a positive polarity, i.e., satisfies Vdata≧Vcom101 in the first frame. It is assumed that, in a second frame, an electric potential that is equal to or lower than the electric potential Vcom101 is applied to the node na and the node nb during light emission of the liquid crystal panel, contrary to the first frame. That is, it is assumed that a voltage (liquid crystal applied voltage) of a negative polarity is applied between the node na and the common electrode com101 and between the node nb and the common electrode com101. In the second frame, the electric potential Vdata supplied from the data driver to the data line S1 has a negative polarity, i.e., satisfies Vdata≦Vcom101.
Similarly, in odd-numbered frames, a voltage Vdata which satisfies Vdata≧Vcom101 is supplied to the data line S1 so that a liquid crystal applied voltage of a positive polarity is applied between the node na and the common electrode com101 and between the node nb and the common electrode com101. In even-numbered frames, a voltage Vdata which satisfies Vdata≦Vcom101 is supplied to the data line S1 so that a liquid crystal applied voltage of a negative polarity is applied between the node na and the common electrode com101 and between the node nb and the common electrode com101.
In FIG. 19, the first frame starts at a time t0a, and an electric potential of the scanning line G0 changes from VGL to VGH at the time t0a. In the first frame, the electric potential Vdata having a positive polarity with respect to the electric potential Vcom101 is supplied to the data line S1 so that the electric potential having a positive polarity with respect to the electric potential Vcom101 is applied to the nodes na and nb, as described above. In FIG. 19, the electric potential Vdata of a positive polarity is represented by “Vdata(+)”. The electric potential of the scanning line G1 returns to VGL by a time t1a that is 1 horizontal period after the time t0a. It is assumed that an electric potential of the node nc is β.
Next, at the time t1a, an electric potential of the scanning line G2 changes from VGL to VGH. This causes the transistors T101 and T102 of a pixel PIX corresponding to i=2 to turn on. Accordingly, the electric potential Vdata of the data line S1 at this time (in this case, Vdata(+)) is applied to the nodes na and nb. Since an electric potential of the scanning line G3 is VGL at this time, the transistor T103 maintains an OFF state. This state continues until a time t2a. This state of the pixel PIX100 is illustrated in FIG. 20.
The electric potential of the scanning line G2 returns from VGH to VGL by the time t2a that is 1 horizontal period after the time t1a. This causes the transistors T101 and T102 to be in an OFF state. Since the transistor T101 is in an OFF state, the electric potential of the node na of the subpixel PIXa is fixed to Vdata (in this case, Vdata(+)). This state of the pixel PIX100 is illustrated in FIG. 21.
Next, at the time t2a, an electric potential of the scanning line G3 changes from VGL to VGH. This causes the transistor T103 to be in an ON state. Since the transistor T102 is in an OFF state and the transistor T103 is in an ON state at this time, a positive electric charge is discharged from the storage capacitor CstB to the buffer capacitor Cdown. Since an odd-numbered frame is described here, it is presumed that the electric potential β of the node nc is lower than the electric potential Vdata of the node nb. Note, however, that in an even-numbered frame, the electric potential β of the node nc is higher than the electric potential Vdata of the node nb. Here, the electric potential of the node nb declines by α (α>0) due to the discharge. As a result, the electric potential of the node nb becomes Vdata-α (in this case, Vdata(+)-α). This state of the pixel PIX100 is illustrated in FIG. 22.
Note that α is determined depending on a capacitance ratio between the storage capacitor CstB and the buffer capacitor Cdown and on the electric potential of the node nc in a previous frame.
The electric potential of the scanning line G3 returns from VGH to VGL by a time t3a that is 1 horizontal period after the time t2a. This causes the transistor T103 to be in an OFF state. Accordingly, the electric potential Vdata-α is retained in the node nb of the subpixel PIXb, and the node nb of the subpixel PIXb maintains this electric potential until a next frame (time t1b). This state of the pixel PIX100 is illustrated in FIG. 23.
After elapse of a remaining time t4a of the first frame, the second frame starts.
In FIG. 19, the second frame starts at the time t0b, and the electric potential of the scanning line G1 changes from VGL to VGH at the time t0b. In the second frame, the electric potential Vdata having a negative polarity with respect to the electric potential Vcom101 is supplied to the data line S1 so that the electric potential having a negative polarity with respect to the electric potential Vcom101 is applied to the nodes na and nb, as described above. In FIG. 19, the electric potential Vdata of a negative polarity is represented by “Vdata(−)”. The electric potential of the scanning line G1 returns to VGL by a time t1b that is 1 horizontal period after the time t0b. 
Next, at the time t1b, an electric potential of the scanning line G2 changes from VGL to VGH. This causes the transistors T101 and T102 of the pixel PIX100 corresponding to i=2 to be in an ON state. Accordingly, the electric potential Vdata of the data line S1 at this time (in this case, Vdata(−)) is applied to the nodes na and nb. At this time, the transistor T103 maintains an OFF state since an electric potential of the scanning line G3 is VGL. This state continues until a time t2b. This state of the pixel PIX100 is illustrated in FIG. 20.
The electric potential of the scanning line G2 returns from VGH to VGL by the time t2b that is 1 horizontal period after the time t1b. This causes the transistors T101 and T102 to be in an OFF state. Since the transistor T101 is in an OFF state, the electric potential of the node na of the subpixel PIXa is fixed to Vdata (in this case, Vdata(−)). This state of the pixel PIX100 is illustrated in FIG. 21.
Next, at the time t2b, an electric potential of the scanning line G3 changes from VGL to VGH. This causes the transistor T103 to be in an ON state. Since the transistor T2 is in an OFF state and the transistor T103 is in an ON state at this time, a positive electric charge is discharged from the buffer capacitor Cdown to the storage capacitor CstB. Since an even-numbered frame is described here, it is presumed that the electric potential β of the node nc is higher than the electric potential Vdata of the node nb. Here, the electric potential of the node nb rises by α (α>0) due to the discharge. As a result, the electric potential of the node nb becomes Vdata+α (in this case, Vdata(−)+α). This state of the pixel PIX100 is illustrated in FIG. 22.
The electric potential of the scanning line G3 returns from VGH to VGL by a time t3b that is 1 horizontal period after the time t2b. This causes the transistor T103 to be in an OFF state. Accordingly, the electric potential Vdata+α is retained in the node nb of the subpixel PIXb, and the node nb of the subpixel PIXb maintains this electric potential during a remaining time t4b until a next frame. This state of the pixel PIX100 is illustrated in FIG. 23.
Subsequently, in odd-numbered frames, a circuit operation of the pixel PIX100 similar to that of the first frame is repeated, and in even-numbered frames, a circuit operation of the pixel PIX100 similar to that of the second frame is repeated.
According to the arrangement of the pixel PIX100, both in an odd-numbered frame and an even-numbered frame, a difference can be produced between a liquid crystal applied voltage retained in the subpixel PIXa and a liquid crystal applied voltage retained in the subpixel PIXb. This allows an improvement in viewing angle characteristic of a liquid crystal panel. Since it is possible to produce a difference in liquid crystal applied voltage between the subpixel PIXa and the subpixel PIXb with the use of an identical electric potential Vdata, the subpixel PIXa and the subpixel PIXb become regions that are different from each other in threshold voltage.